Modern deep sub-micron digital integrated circuits (“ICs”) at 50 nanometers (“nm”) and smaller and systems on chip (“SOC”) exhibit very high transistor density and a need for tight voltage regulation of low voltages at semiconductor die pads internal to the integrated circuit, rather than at physical circuit nodes external to the integrated circuit package. The deep sub-micron integrated circuits, such as digital integrated circuits, and systems on chips that operate at input or bias voltages such as 1.2 volts or less can exhibit high sensitivity to interfering voltages induced into the integrated circuit or systems on chips. Hence, it is advantageous to provide point-of-load power conversion and regulation at the semiconductor die level. This is presently achieved in the integrated circuits by incorporating linear voltage regulators with low drop-out (“LDO”) voltages within an integrated circuit package. A drawback of using such linear voltage regulators is higher than desired chip power dissipation due to the dissipative voltage drop thereacross resulting in low power conversion efficiencies, typically in the 20-50 percent range.
Alternatively, switch-mode regulators provide the same voltage conversion capability at much higher efficiencies, typically in the 80-95 percent range, thereby reducing power dissipation by a factor of two or three. To date, however, the switch-mode regulators have not been incorporated into high density integrated circuits due to a mismatch in technologies. This is particularly true with the generation of high-frequency electromagnetic interference, and in silicon fabrication, packaging, assembly, and test, which are all challenging areas, principally for fabrication of digital integrated circuits such as field programmable gate arrays (“FPGAs”) constructed with sub-micron structures of dimensions 50 nanometers and less.
What is needed in the art is a technique to integrate a switch-mode regulator with an integrated circuit such as a sub-50 nanometers digital integrated circuit so that it can provide localized, point-of-load regulation at the semiconductor level while maintaining compatibility with silicon assembly and test technologies in a manner that does not introduce intolerable levels of interfering voltages in the integrated circuit package. Due to proximity to the load, silicon noise considerations are a concern, which can be even more challenging than board-level voltage regulation. Techniques to remove, reduce, or otherwise eliminate noise at the semiconductor die level are important, particularly for system on chips that employ sensitive, high speed circuits. A packaged integrated circuit constructed with a switch-mode regulator that does not introduce intolerable levels of circuit noise in nearby circuit elements of the integrated circuit would address an unanswered industry need.